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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
oki semiconductor fedl9227-01 issue date:dec., 18, 2002 ml9227 27-bit duplex/triplex vfd co ntroller/driver with digita l dimming, adc and key scan 1/26 general description the ml9227 is a full cmos controller/driver for duplex or triplex vacuum fluorescent display tube. it conststs of 27-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 81-segment vfd. ml9227 features a digital dimming function, a 6-ch adc, a 5 5 key scan circuit and an encoder type switch interface. ml9227 provides an interface with a microcontroller onl y by three signal lines: data i/o, clock, cs. features ? supply voltage (v disp ) : 8 to 18.5 v (built-in 5 v regulator for logic) ? duplex/triplex selectable ? applicable vfd tube : 2 grids 27 anodes vfd tube : 3 grids 27 anodes vfd tube ? 27-segment driver outputs : i oh = ?5 ma at v oh = v disp ?0.8 v (seg1 to 19) i oh = ?10 ma at v oh = v disp ?0.8 v (seg20 to 27) i ol = 500 ua at v ol = 2.0 v (seg1 to 27) ? 3-grid pre-driver outputs : i oh = ?5 ma at v oh = v disp ?0.8 v i ol = 10 ma at v ol = 2.0 v ? built-in digital dimming circuit (10-bit resolution) ? built-in 6-ch a/d converter ? built-in 5 5 keyscan circuit ? interface circuit for an encoder type rotary switch ? built-in oscillation circuit (external r and c) ? built-in power-on-reset circuit ? package: 64-pin plastic qfp (qfp64-p-1420-1.00-bk) product name: ML9227GA
fedl9227-01 oki semiconductor ml9227 2/26 block diagram sync out1 sync out2 timing generator dim out dup/ tri osc control out1-27 27 bit shift register in1-10 dimming latch out1-10 10 bit digital dimming por cs clock data i/o out1-3 3 bit shift register por por por 4h out1-27 segment latch 3 in1-27 0h 3h por out1-27 segment latch 2 in1-27 0h 2h por out1-27 segment latch 1 in1-27 0h 1h por mode select in1-3 por 0h 7h 5 v regulator & power on reset v cc (5 v) l-gnd por out1-27 81 to 27 segment control in1-27 in1-27 in1-27 27 segment driver d-gnd v disp 3 grid pre driver g rid 2 grid 3 g rid 1 seg27 seg1 vreg (5 v) 5 5 key scan and encoder switch interface int 6ch, 8 bit a/d converter osc0 ch1 ch6 c ol 1 c ol 5 row1 row5 a1 b1 5h 6h 7h
fedl9227-01 oki semiconductor ml9227 3/26 pin configuration (top view) nc: no connection (open) 64-pin plastic qfp seg17 seg22 seg23 seg24 64 63 62 61 60 59 58 57 56 55 54 53 52 seg16 seg18 seg19 seg21 seg20 seg15 seg14 seg13 seg12 l-gnd 20 a1 21 b1 22 int 23 dup/ tr i 24 v cc 25 osc0 26 27 28 29 30 31 32 data i/o cloc k cs sync out2 sync out1 dim out 48 49 50 51 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg10 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ch6 ch5 seg9 ch4 ch3 ch2 ch1 vreg v disp seg11 15 16 17 18 19 4 3 2 1 5 6 7 8 9 10 11 12 13 14 c ol 2 c ol 3 c ol 4 c ol 5 nc v disp seg25 seg26 seg27 g rid 1 g rid 2 g rid 3 d-gnd row1 row2 row3 row4 row5 c ol 1
fedl9227-01 oki semiconductor ml9227 4/26 pin descriptions pin symbol type description 1, 51 v disp ? power supply pins pin1 and pin51 should be connected externally. 8 d-gnd ? 26 l-gnd ? d-gnd is ground pin for the vfd driv er circuit. l-gnd is ground pin for the logic circuit. pins 8 and 26 should be connected externally. 24 v cc o 5 v output pin for internal logi c portion and external logic circuit 33 v reg o reference voltage (5 v) output pin for a/d converter 40 to 50, 52 to 59 seg1 to 19 o segment (anode) signal output pins for a vfd tube these pins can be directly connected to the vfd tube. external circuit is not required. l oh ?5 ma 60 to 64, 2 to 4 seg20 to 27 o segment (anode) signal output pins for a vfd tube these pins can be directly connected to the vfd tube. external circuit is not required. l oh ?10 ma 5, 6, 7 grid 1 to 3 o inverted grid signal output pins for pre-driver, the external circuit is required. l ol 10 ma 29 cs l chip select input pin data input/output operation is valid when this pin is set at a high level. 28 clock l serial clock input pin data is input and/or output through t he data l/o pin at the rising edge of the serial clock. 27 data l/o l/o serial data input/output pin data is input to/comes out from the shift register at the rising edge of the serial clock. 22 int o interrupt signal output to micro contro ller. when any key of key matrix is pressed or released, key scanning is started. after the completion of the one cycle, this pin goes to high level and keeps the high level until key scan stop mode is selected. 23 dup/ trl l duplex/triplex operation select input pin duplex (1/2 duty) operation is selected when this pin is set at a v cc level. triplex (1/3 duty) operation is sele cted when this pin is set at a gnd level. 34 to 39 ch1 to 6 l analog voltage input pin for the 8-bit a/d converter 20, 21 a1, b1 o input pin for the encoder type rotary switch. the phase of an an/bn input is detected. 14 to 18 col 1 to 5 l return inputs from the key matrix these pins are active low. when key matrix are in the inactive sate, these pins are at high level through t he internal pull-up resistors. all the inputs do not have the chattering absor ption function for the key scans. 9 to 13 row1 to 5 o key switch scanning outputs normally low level is output through t hese pin. when any switch of key matrix is depressed or released, key scanning is started and is continued until key scan stop mode is select ed. when key scan stop mode is selected, all outputs of row1 to 5 go back to low level.
fedl9227-01 oki semiconductor ml9227 5/26 pin symbol type description 32 dim out o dimming pulse output connect this pin to the slave side dim in pin. 30, 31 sync out 1, 2 o synchronous signal input connect these pins to the sync in1 a nd sync in2 pins of a slave side. 25 osc0 l/o rc oscillator connecting pins. oscillation frequency depends on display tubes to be used. for details refer to electrical characteristics. 19 nc - open pins. v cc osc0 r co
fedl9227-01 oki semiconductor ml9227 6/26 absolute maximum ratings parameter symbol condition rating unit supply voltage v disp ? ?0.3 to +20 v input voltage v in ? ?0.3 to +6.0 v power dissipation p d ta = 85 c qfp64-p-1420-1.00-bk 250 mw storage temperature t stg ? ?55 to +150 c l o1 seg1 to 19 ?10.0 to +2.0 ma l o2 seg20 to 27 ?20.0 to +2.0 ma l o3 grid 1 to 3 ?10.0 to +20.0 ma output current l o4 dim out, sync out1, sync out2 ?2.0 to +2.0 ma recommended operating conditions parameter symbol condition min. typ. max. unit driver supply voltage v disp ? 8.0 13.0 18.5 v high level input voltage v ih all inputs except osc0 3.8 ? ? v low level input voltage v il all inputs except osc0 ? ? 0.8 v clock frequency f c ? ? ? 2.0 mhz oscillation frequency f osc r = 10 k ? 5%, co= 27 pf 5% 2.2 3.3 4.4 mhz 1/3 duty 179 269 358 hz frame frequency f fr r = 10 k ? 5% co = 27 pf 5% 1/2 duty 268 403 538 hz operating temperature t op ? ?40 ? +85 c
fedl9227-01 oki semiconductor ml9227 7/26 electrical characteristics dc characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter symbol applied pin condition min. max. unit high level input voltage v ih *1) ? 3.8 ? v low level input voltage v il *1) ? ? 0.8 v l ih1 *2) v ih = 3.8 v ?5.0 +5.0 a high level input current l ih2 *3) v ih = 3.8 v ?70 ?5.0 a l il1 *2) v il = 0.0 v ?5.0 +5.0 a low level input current l il2 *3) v il = 0.0 v ?160 ?10 a v oh1 seg1 to 19 l oh1 = ?5 ma v disp ?0.8 ? v v oh2 seg20 to 27 l oh2 = ? 10 ma v disp ?0.8 ? v v oh3 grid 1 to 3 l oh3 = ?5 ma v disp ?0.8 ? v l oh4 = ?200 a 4.0 ? v high level output voltage v oh4 *4) v disp = 9.5v output open 4.5 ? v v ol1 seg1 to 19 l ol1 = 500 a ? 2.0 v v ol2 seg20 to 27 l ol2 = 500 a ? 2.0 v v ol3 grid 1 to 3 l ol3 = 10 ma ? 2.0 v low level output voltage v ol4 *5) v disp = 9.5v l ol4 = 300 a ? 0.4 v supply current i disp v disp r = 10 k ? 5%, co= 27 pf 5% no load ? 10 ma supply voltage for logic v l v cc c = 0.01 f 10%, l o = 0 to ?10 ma 4.5 5.5 v *1) cs, clock, data i/o, dup/ tri , a1, b1, col 1 to 5 *2) cs, clock, data i/o, dup/ tri , a1, b1 *3) col 1 to 5 *4) data i/o, int, dim out, sync out1, sync out2 *5) data i/o, int, dim out, sync out1, sync out2, row1 to 5
fedl9227-01 oki semiconductor ml9227 8/26 ac characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter symbol condition min. max. unit clock frequency f c ? ? 2.0 mhz clock pulse width t cw ? 200 ? ns data setup time t ds ? 200 ? ns data hold time t dh ? 200 ? ns cs off time t csl r = 10 k ? 5%, co = 27 pf 5% 20 ? s cs setup time (cs-clock) t css ? 200 ? ns cs hold time (clock-cs) t csh ? 200 ? ns data output delay time (clock-data l/o) t pd ? ? 1.0 s t r t r = 20 to 80% ? 2.0 s output slew rate time t f c l =100 pf t f = 80 to 20% ? 2.0 s v dd rise time t prz mounted in a unit ? 100 s v dd off time t pof mounted in a unit, v disp = 0.0 v 5.0 ? ms cs wait time t rsoff ? 400 ? s
fedl9227-01 oki semiconductor ml9227 9/26 timing diagrams data input timing data output timing reset timing driver output timing ?3.8 v ?0.8 v ?3.8 v ?0.8 v ?3.8 v ?0.8 v cs clock data i/o (input) t ds t dh t css 1/f c t cw t cw t csh t csl valid valid valid valid ?3.8 v ?0.8 v ?3.8 v ?0.8 v ?3.8 v ?0.8 v cs clock data i/o (output) t pd t css t csh t pof t prz v disp cs t rsoff ?0.8 v disp ?0.0 v ?3.8 v ?0.0 v ?0.8 v disp ?0.2 v disp seg1-27, grid 1-3 t r t f
fedl9227-01 oki semiconductor ml9227 10/26 a/d converter characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter condition min. typ. max. unit reference voltage (v reg ) ? 4.5 5.0 5.5 v output current ? ? ? ?10 ma input voltage range ? gnd ? v reg v conversion time/channel r = 10 k ? 5%, c2 = 27 pf 5% 256 310 394 s resolution ? ? 8 bit linearity error ? ? 2.0 lsb differentiation linearity error ? ? 2.0 lsb zero scale error ? ? +2.0 lsb full-scale error ? ? -2.0 lsb terminological definition resolution the minimum input analog value which can be recognized. it can decompose into 2 8 = 256,(v rh -v rl )/256,in 8 bits. linearity error the deviation between the ideal conver sion characteristic as a 8-bit a /d converter and the actual conversion characteristic is said. (therefore, a quantization erro r is not included.) the ideal conversion characteristic means t he step which divided the voltage between v rh to v rl into 256 division into equal parts. differentiation linearity error the smoothness of the conversion ch aracteristic is shown, and ideally, the width of the anal og input voltage corresponding to change for 1 bit of digital outputs is 1lsb= (v rh -v rl )/256, and says the deviation of this ideal bit size and the bit size in the arbitrar y points of the conversion range. zero scale error digital output "000h" to "001h" c hanges, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said . full scale error digital output "0feh" to "0ffh" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said.
fedl9227-01 oki semiconductor ml9227 11/26 key scan characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter condition min. typ. max. unit key scan cycle time r = 10 k ? 5%, co = 27 pf 5% 160 194 246 s key scan pulse width r = 10 k ? 5%, co = 27 pf 5% 32 39 49 s rotary switch characteristic (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter sign condition min. typ. max. unit phase input time t abw phase input fixed time t abh r = 10 k ? 5%, co = 27 pf 5% 950 ? ? s rotary switch input timing a b key scan timing row1 row5 row2 row3 row4 key scan cycle time key scan pulse width tabw tabw tabw tabw tabh tabh
fedl9227-01 oki semiconductor ml9227 12/26 output timming(duplex operation) *1 bit time = 4/f osc solid line : the dimming data is 1016/1024 dotted line : the dimming data is 64/1024 output timming(triplex operation) *1 bit time = 4/f osc solid line : the dimming data is 1016/1024 dotted line : the dimming data is 64/1024 g rid 1 v disp d-gnd g rid 2 v disp d-gnd g rid 3 seg1-27 v disp d-gnd dim out 5v l-gnd sync out1 5v l-gnd sync out2 5v l-gnd v disp d-gnd 1016 bit times 1016 bit times 1016 bit times 2048 bit times(1 display cycle) 8 bit times 8 bit times 8 bit times 64 bit times 64 bit times 64 bit times g rid 1 v disp d-gnd g rid 2 v disp d-gnd g rid 3 seg1-27 v disp d-gnd dim out 5v l-gnd sync out1 5v l-gnd sync out2 5v l-gnd v disp d-gnd 1016 bit times 1016 bit times 1016 bit times 3072 bit times(1 display cycle) 8 bit times 8 bit times 8 bit times 64 bit times 64 bit times 64 bit times
fedl9227-01 oki semiconductor ml9227 13/26 functional description power-on reset when power is turned on, ml9227 is initialized by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: ? the contents of the shift regist ers and latches are set to ?0?. ? the digital dimming duty cycle is set to ?0?. ? all segment outputs are set to low level. ? grid 1 outputs are set to low level. ? grid 2 to 3 outputs are set to high level. ? all the row outputs are set to low level. ? int output is set to low level. mode data ml9227 has the seven function modes. the function mode is selected by the mode data (m0 to m2). the relation between function mode and mode data (m0 to m2) is as follows: function data function mode operating mode m0 m1 m2 0 segment data for grid 1-3 input 0 0 0 1 segment data for grid 1 input 1 0 0 2 segment data for grid 2 input 0 1 0 3 segment data for grid 3 input 1 1 0 4 digital dimming data input 0 0 1 5 key scan stop 1 0 1 6 switch data output 0 1 1 7 a/d data output 1 1 1 data input and output data input and output through the data-i/o pin is valid only when the cs pin is set at a high level. the input data to data i/o pin is shifted into the shift regi ster at the rising edge of the serial clock. the data is automatically loaded to the latches when the cs pin is set at a low level. 10-bit dimming data (d1 to d10) and 27-bit segment data (s1 to s27) are used for inputting of dimming data and display data. to transfer these two data, the mode data (m0 to m2) must be sent after each of these data succeddingly. the output data from the data i/o pin is output from the shift register at the rising edge of the serial clock. ml9227 outputs 48-bit (6ch 8bits) a/d data (a11 to a68) and 29-bit key data (s11 to s55, r1 and q1 to q3). to receive these data, the mode data (m0 to m2) must be sent first and then cs must be set once to low level and set again to high level. then inputting serial clocks, these data are output from the data i/o pin. when the cs pin is set at a low level, the data i/o pin returns to an input pin. to stop the keyscan, the only mode data (m0 to m2) must be sent. after the mode data transfer, the key scanning is stopped immediately.
fedl9227-01 oki semiconductor ml9227 14/26 segment data input [function mode: 0 to 3] ? ml9227 receives the segment data when function mode 0 to 3 are selected. ? the same segment data is transferred to the 3 segment data latch correspond to grid 1 to 3 at the same time when the function mode 0 is selected. ? the segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. ? segment output (seg1 to 27) becomes high level when the segment data (s1 to 27) is high level. [data format] input data : 30 bits segment data : 27 bits mode data : 3 bits bit 1 2 3 4 ----------- 24 25 26 27 28 29 30 input data s1 s2 s3 s4 ----------- s24 s25 s26 s27 m0 m1 m2 mode data (3 bits) [bit correspondence between segment output and segment data] seg n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 segment data s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 seg n 17 18 19 20 21 22 23 24 25 26 27 segment data s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 segment data (27 bits ) lsb msb
fedl9227-01 oki semiconductor ml9227 15/26 digital dimming data input [function mode: 4] ? ml9227 receives the digital dimming data when function mode 4 is selected. ? the output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. ? the 10-bit digital dimming data is input from lsb. [data format] input data : 13 bits digital dimming data : 10 bits mode data : 3 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 13 input data d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 m0 m1 m2 lsb msb digital dimming data (10 bits) mode data (3 bits) (lsb) dimming data (msb) d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 duty cycle 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 key scan stop [function mode: 5] ? ml9227 stops a key scanning when function mode 5 are selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? the actual time lag range between receipt of the ke yscan stop command and the ceasing of scanning is 2.4 s to 3.6 s [input data format] input data : 3 bits mode data : 3 bits bit 28 29 30 input data m0 m1 m2 mode data (3 bits)
fedl9227-01 oki semiconductor ml9227 16/26 switch data output [function mode: 6] ? ml9227 output the switch data when function mode 6 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9227 recieves this mode, the data i/o pin is changed to an output pin. ? 29-bit switch data come out from the data i/o pin synchronizing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. ? r1 = 0, implies right rotation of the knob (clockwise) ? r1 = 1, implies left rotation of the knob (counter clockwise) ? contact count bits are q1 (lsb) to q3 (msb) [input data format] input data : 3 bits mode data : 3 bits bit 28 29 30 input data m0 m1 m2 mode data (3 bits) [output data format] output data : 29 bits 5 5 push switch data : 25 bits encoder switch data : 4 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 output data s11 s12 s13 s14 s15 s21 s22 s23 s24 s25 s31 s32 s33 s34 s35 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 output data s41 s42 s43 s44 s45 s51 s52 s53 s54 s55 r1 q1 q2 q3 sij: i = row1 to 5, j = col 1 to 5 sij = 1: switch on sij = 0: switch off [5 5 push switch] c ol1 s11 s21 s31 s41 s12 s22 s32 s42 s13 s23 s33 s43 s14 s24 s34 s44 s51 s52 s53 s54 s55 c ol2 c ol3 c ol4 s15 s25 s35 s45 c ol5 row1 row2 row3 row4 row5
fedl9227-01 oki semiconductor ml9227 17/26 key scan keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. the int pin goes to the high level at the completion of 1-cycl e scanning after the keyscan start, so the (high level) signal sent from the int pin can be used as an interrupt signal. [key scan timing] note: key scanning cannot be stopped by selecting the key scan stop mode only once if: - key scanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the key scan stop mode is selected. to stop key scanning, it is required to select the key scan stop mode once again. 1 cycle int row 4 row 3 row 2 row 1 row 0 depress/release key scan stop mode is selected. depress depress release key scan key scan int cs mode5 mode5 mode5 mode5 : key scan stop
fedl9227-01 oki semiconductor ml9227 18/26 a/d data output [function mode: 7] ? ml9227 output the a/d data when function mode 7 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9227 recieves this mode, the data i/o pin is changed to an output pin. ? 48-bit a/d data come out from the data i/o pin synchronizeing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. [input data format] input data : 3 bits mode data : 3 bits bit 28 29 30 input data m0 m1 m2 mode data (3 bits) [output data format] output data : 48 bits a/d data : 48 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 output data a11 (lsb) a12 a13 a14 a15 a16 a17 a18 (msb) a21 (lsb) a22 a23 a24 a25 a26 a27 a28 (msb) a/d ch1 ch2 bit 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 output data a31 (lsb) a32 a33 a34 a35 a36 a37 a38 (msb) a41 (lsb) a42 a43 a44 a45 a46 a47 a48 (msb) a/d ch3 ch4 bit 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 output data a51 (lsb) a52 a53 a54 a55 a56 a57 a58 (msb) a61 (lsb) a62 a63 a64 a65 a66 a67 a68 (msb) a/d ch5 ch6
fedl9227-01 oki semiconductor ml9227 19/26 the rotary encoder switch function as figure 1 shows, the rotary encoder switch circuit is consisted of phase detection, interrupt generation, up/down counter, direction latch and parallel-in serial-out shift register. figure 1 the rotary encoder switch circuit 1) phase detection 1-1) clockwise when signal a and b input as figure 2, the phase detectio n circuit outputs up signal after the chattering absorption period. at this time, the output int also goes to high level, so this signal can be used as an interrupt. the int stays high level until the keyscan stop mode is selected. figure 2 the input and output timing in case of clockwise phase detection up down b q3 q2 q1 a up/down counter p-in/s-out shift register r1 direction latch interrupt generation for int output data up (internal) b a int chattering absorption time
fedl9227-01 oki semiconductor ml9227 20/26 1-2) counter clockwise when signal a and b input as figure 3, the phase detection circuit outputs down signal after the chattering absorption period. at this time, the output int also goes to high level. the int stays high level until the keyscan stop mode is selected. figure 3 the input and output timing in case of counter clockwise 2) up/down counter when the up/down counter is input up, it counts up and when it is input down, it counts down. but if overcounte of ?111? occurs the up/down counter stays ?111?. figure 4 3) direction latch when the direction latch is input down the output r goes ?1?. but if the up pulse is input and the counts value change to plus value, the output r goes to ?0?. figure 5 down (internal) b a int chatterin g absor p tion time b q1, q2, q3 a 100 010 110 001 101 011 111 111 b q1, q2, q3 a 010 100 100 100 000 010 r1
fedl9227-01 oki semiconductor ml9227 21/26 4) p-in/s-out shift resistor when the keyscan stop mode is selected and cs goes l, int signal goes ?l?. figure 6 cs data i/o clock int signal goes ?l?. int c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 row1 row2 row5 rotary c1 c2 c3 c4 c5 r1 q1 q2 q3
fedl9227-01 oki semiconductor ml9227 22/26 application circuits 1. circuit for the duplex vfd tube with 118 segments (2 grid 59 anode) ml9227 v disp v cc l-gnd osc0 v cc clock data i/o cs vreg dup/ tri dim out sync out 1 sync out 2 grid 2 grid 1 grid 3 seg1 seg27 ml9213 (slave) v disp v dd l-gnd osc 0 osc 1 clock data in cs dim in sync in 1 sync in 2 dim out sync out 1 sync out 2 grid 2 grid 1 grid 3 seg1 seg56 duplex vfd tube s57 s58 s59 s1 s2 s3 g1 g2 v disp m/ s gnd dup/ tri ef gnd gnd gnd ch1 to 6 row1 to 5 c ol 1 to 5 5 5 key matrix micro controller (master)
fedl9227-01 oki semiconductor ml9227 23/26 2. circuit for the triplex vfd tube with 177 segments (3 grid 59 anode) ml9227 v disp v cc l-gnd clock data i/o cs dim out sync out 1 sync out 2 grid 2 grid 1 grid 3 seg1 seg27 ml9213 (slave) v disp v dd l-gnd osc 0 osc 1 clock data in cs dim in sync in 1 sync in 2 m/ s dup/ tri dim out sync out 1 sync out 2 grid 2 grid 1 grid 3 seg1 seg56 triplex vfd tube s57 s58 s59 s1 s2 s3 g1 g2 v disp gnd ef gnd gnd gnd osc0 v cc gnd ch1 to 6 row1 to 5 c ol 1 to 5 5 5 key matrix vreg g3 dup/ tri micro controller (master)
fedl9227-01 oki semiconductor ml9227 24/26 package dimensions qfp64-p-1420-1.00-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.25 typ. 5 rev. no./last revised 4/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respons ible sales person for the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl9227-01 oki semiconductor ml9227 25/26 revision history page document no. date previous edition current edition description fedl9227-01 dec., 18, 2002 ? ? final edition 1
fedl9227-01 oki semiconductor ml9227 26/26 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improp er handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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